Turning to FIG. 1, a cross-sectional view of a conventional high voltage capacitor CS1 (i.e. >40V) is shown. As shown, this capacitor CS1 is formed of multiple parallel-plate capacitors in what can be referred to as a “sandwich” capacitor. In this configuration, there are three intended parallel-plate capacitors that are formed by: (1) metallization layer 118, dielectric layer 116, and metallization layer 114; (2) metallization layer 114, dielectric layer 112, and metallization layer 110; and (3) metallization layer 110, dielectric layer 108, and polysilicon layer 106. There is also a parasitic capacitor CPAR1 (which is shown in FIG. 2) formed by polysilicon layer 106, dielectric layer 104, and substrate 102. By electrically coupling metallization layers 118 and 110 together, one electrode for capacitor CS1 can be formed at node N1. Additionally, by electrically coupling metallization layer 110 to polysilicon layer 106 at node N2 another electrode for capacitor CS1 can be formed.
In some applications, it may be desirable to use high voltage capacitor CS1 where one plate (namely, polysilicon layer 106) is not tied to the substrate potential. An example of such a circuit can be seen in FIG. 2. For the circuit in IC 201 in system 200, it measures a current flowing through transistor Q1 (where its gate is electrically coupled to pin CNTL). Transistor Q2 is a smaller ration sense FET so that, when current traverses transistor Q2 and resistor R1, amplifier 202 can measure the current. Capacitor CS1 would then provide a filtering function and would not be tied to the substrate potential.
As part of the testing and verification process normally employed for semiconductors, some components are subjected to OVST to accelerate latent defects that may be present from manufacturing. Looking to IC 201 as an example, parasitic capacitor CPAR1 would be subjected to OVST, where the latent defect is the cone defect 120 in dielectric layer 104. For capacitor CS1, the dielectric layer 104 can be referred to as an isolation layer and is generally formed through a shallow trench isolation or STI etching process. Namely, because the substrate 102 generally includes a P-type epitaxial layer, micro-defects (called “cone defects”) can “grow” in the epitaxial layer, reducing the thickness of layer 104 at the point of the cone defect. During testing, a high voltage (i.e., 60% greater than the voltage rating of the capacitor CS1) should be applied to capacitor CPAR1 to determine whether capacitor CPAR1 will fail at lower than expected voltages (which could cause functional problems with IC 201) due at least in part to these cone defects.
One problem with this arrangement, however, is that OVST may be difficult to perform. Referring back to the circuit in IC 102, capacitor CS1 is not tied to the substrate potential. This means that components in IC 201 (i.e., transistors Q1 and Q2) would be subjected to the full OVST voltage. Now, assuming, for example, that pin BAT has a 40V rating, the voltage rating on capacitor CS1 can be as high as 80V, which can, for example, place a 60% OVST voltage (i.e., 128V) stress requirement on capacitor CPAR1 to assure capacitor quality. As a result, the components (i.e., transistors Q1 and Q2) would normally also be subjected to 128V in this example if capacitor CPAR1 is subjected to the 60% OVST voltage. Since, however, the pin BAT is rated at 40V in this example, the corresponding components (i.e., transistors Q1 and Q2) are designed to be 45-50V components, meaning that these components (i.e., transistors Q1 and Q2) cannot tolerate 128V. Thus, there is a need for a capacitor that can be subjected to high OVST voltages independent from other components in the IC.
Some examples of conventional systems are: U.S. Pat. No. 8,026,177; U.S. Patent Pre-Grant Publ. No. 2009/0166875; and U.S. Patent Pre-Grant Publ. No. 2009/0250784.pdf